BTR Board

Tech Specs:

Uses an FME-7, made by Sunsoft.
Max. 512K PRG ROM.
Max. 256K CHR ROM.


This board is similar to an MMC3 board, except the mapper is different. It uses an FME-7 chip. This chip does the usual memory mapping, but it also has sound on it. Unfortunately, the sound is not used and I am not sure how it hooks up, because I do not possess a Famicom cart with the same mapper to trace it out. This mapper has the same 220pf cap on the CHR A12 line like the MMC3 has.

FME-7 Packaging Information

FME-7 comes in a 44 pin TQFP package

FME-7 Pinout:

                           33     23
                            |     |
                        34-|       |-22
                           | FME-7 |
                        44-|       |-12
                            |     |
                            1     11

Pin# Function      Pin# Function
---- --------      ---- --------

1  - PRG D3  (s)   23 - CHR A12 (r)
2  - PRG A18 (r)   24 - CHR A14 (r)
3  - NC            25 - CHR A15 (r)
4  - M2 (n)        26 - CHR A17 (r)
5  - PRG A13 (n)   27 - +5V
6  - GND           28 - GND
7  - PRG A14 (n)   29 - PRG +CE (w)
8  - PRG /CE (n)   30 - PRG /CE (w)
9  - PRG R/W (s)   31 - PRG /CE (r)
10 - /IRQ (n)      32 - PRG A17 (r)
11 - CHR /RD (n)   33 - PRG A15 (r)

12 - CHR A10 (n)   34 - PRG A14 (r)
13 - CHR A11 (n)   35 - PRG A16 (r)
14 - CHR A12 (n)   36 - PRG A13 (r)
15 - CHR /A13 (n)  37 - PRG D7 (s)
16 - CHR /CE (r)   38 - PRG D6 (s)
17 - +5V           39 - +5V
18 - NC            40 - PRG D0 (s)
19 - CHR A10 (r)*  41 - PRG D5 (s)
20 - CHR A16 (r)   42 - PRG D1 (s)
21 - CHR A11 (r)   43 - PRG D4 (s)
22 - CHR A13 (r)   44 - PRG D2 (s)

* - this connection also goes to CIRAM A10

Notes:  The two NC pins (3 and 18) must be for the sound functionality on this mapper,
but I do not have any information about it.  Does someone wanna loan me a Mr. Gimmick
Fami cart for awhile?


This is the control register.

7       0
xxxx SSSS

This selects which mapper register will be written to via register A000h.

0h - 1K CHR ROM bank at PPU 0000-03FFh
1h - 1K CHR ROM bank at PPU 0400-07FFh
2h - 1K CHR ROM bank at PPU 0800-0BFFh
3h - 1K CHR ROM bank at PPU 0C00-0FFFh
4h - 1K CHR ROM bank at PPU 1000-13FFh
5h - 1K CHR ROM bank at PPU 1400-17FFh
6h - 1K CHR ROM bank at PPU 1800-1BFFh
7h - 1K CHR ROM bank at PPU 1C00-1FFFh
8h - 8K PRG ROM bank at CPU 6000-7FFFh
9h - 8K PRG ROM bank at CPU 8000-9FFFh
Ah - 8K PRG ROM bank at CPU A000-BFFFh
Bh - 8K PRG ROM bank at CPU C000-DFFFh
Ch - mirroring control
Dh - IRQ control
Eh - low byte of IRQ counter
Fh - high byte of IRQ counter

(Note: the last 8K of PRG ROM space is hard wired to the last 8K of the PRG ROM.)

This is the data register.

Mapper register 08h is special.  It can map in WRAM as well as PRG ROM.

7       0
ERxx xxxx

E: RAM Enable

1 - turn RAM on
0 - turn RAM off (note: tied to +CE on the WRAM... could be used to address more RAM)

R: bank mode

1 - RAM
0 - ROM

Note: if R is set to 1, and E is set to 0, open bus will be returned for this bank.  Some
carts MAY map more RAM here... this isn't known at this time (due to a lack of carts!).
Also, RAM could simply use more address lines to map in...  potentially up to 256K of it!

Mapper register 0Ch controls mirroring.

7       0
xxxx xxMM

00b - Vertical
01b - Horizontal
10b - 1 Screen (NT 0)
11b - 1 Screen (NT 1)


The interrupt timer is quite simple on this mapper.  It is just a 16 bit down counter.

Mapper registers 0Eh and 0Fh allow writing to the lower and upper 8 bits of it, respectively.
There are no buffers or anything, so the timer must be reloaded each time it is to be used.
The timer decrements once for every M2 clock cycle.  When it reaches 0, the /IRQ is generated.
When the timer expires, it simply wraps to 0ffffh and continues counting.

Mapper register 0Dh controls the IRQ timer:

7       0
Exxx xxxC

E: Timer enable

0 - disable IRQ flag
1 - enable IRQ flag

C: Timer Count enable

0 - stop timer counting
1 - allow timer to count

Note:  Both bits must be set for an /IRQ to be generated.  Clearing either or both bits will
reset the /IRQ flag and deassert the /IRQ line (i.e. ACK the /IRQ).  If bit C is set, the
timer will continue to run, but no interrupts will be generated.

Sound hardware:

C000h - address register
E000h - data register

The sound hardware on this mapper is a clone of the AY-8910.  Not much more to say
about it than that really. (The AY-8911 through AY-8913 use identical sound hardware...
they just have differing amounts of I/O ports on them)

All HTML and graphics designed and copyright by Kevin Horton except chip package illustration.